Semiconductor device and method of enveloping an intergrated circuit

ABSTRACT

A package of a semiconductor device comprising an integrated circuit ( 10 ) generally comprises an inner layer ( 21 ) and an outer layer ( 16 ), which layers ( 16,21 ) have a mutual interface ( 24 ). An improved stability of the package is realized in that the interface ( 24 ) encloses a delamination area ( 22 ), which area ( 22 ) is isolated from any bond pads ( 18 ) of the integrated circuit ( 10 ). The delamination area ( 22 ) may be created by a pattern-wise activation of a surface of the inner layer ( 21 ). A quantity of a curable polymer may be disposed on this surface to achieve this.

The invention relates to a semiconductor device comprising a carrier andan integrated circuit comprising one or more semiconductor elements andone or more connection regions by which the semiconductor elements arecontacted, the circuit being isolated from the environment by anenvelope, said envelope comprising an inner layer and an outer layerwhich have a mutual interface, the carrier comprising electricallyconductive portions by which the connection regions are connected via aconnection means.

The invention also relates to a method of enveloping an integratedcircuit in an envelope comprising an inner layer and an outer layerhaving a mutual interface, which method comprises the steps of disposingthe inner layer on a surface of the integrated circuit, activating asurface of the inner layer, and disposing the outer layer on the surfaceof the inner layer, thus forming the mutual interface.

Such a semiconductor device and such a method are known from JP-A62-185343. The inner layer of the known device comprises a siliconmaterial. The outer layer comprises an epoxy resin filled with quartz orglass powder. Furthermore, interconnect structures are provided. Theconnection means is a bond wire. The integrated circuit is covered witha passivation layer so as to be protected against damage and foulingduring further processing and subsequent useful life. This layerconsists of, for example, one or more layers of phosphorus silicateglass or silicon nitride.

Differences in thermal coefficients of expansion between the material ofthe outer layer and the passivation layer may give rise to largemechanical stresses in the semiconductor device in case of temperaturevariations, more particularly when the dimensions of the integratedcircuit are relatively large. This is the case, for example, when anenvelope of the chip-scale package type is used. These stresses and themicrocracks developed in the passivation layer owing to the stresses maygive rise to damaging of the circuit, so that functional defects andeven breakdown of the semiconductor device may occur. Moisture from theenvironment can reach the circuit through the cracks and cause corrosionthere. In order to reduce said defects, an inner layer of a syntheticresin material, such as polyamide and silicon resin, is customarilyused.

The inner layer of the known device contains microcapsules in order tomake it resistant to the pressure from the outer layer. Closing of theouter layer, which treatment is performed under pressure, raises thetemperature, and the gas present in the microcapsules escapes. This gasforms a cavity between the inner layer and the outer layer of theenvelope.

It is a disadvantage of the known device that the presence of a cavityimposes very stringent requirements on the outer layer. If this outerlayer is not completely sealed at any one point, moisture can reach theconnection regious through the cavity and thus penetrate into theintegrated circuit. In addition, the escaping gas may lead to stresseson the outer layer and damage thereof, more particularly if this escapedoes not take place in a fully controlled manner or if part of the gasescapes at a later stage.

Therefore, it is a first object of the invention to provide asemiconductor device of the type mentioned in the introductory paragraphin which mechanical stresses are reduced.

The first object is achieved in that the mutual interface fully bounds adelamination area as a result of which full bounding the delaminationarea is isolated from the bonding pads. The mechanical stresses can beremoved in a controlled manner by the creation of a delamination area.Since the delamination area is enclosed, there is no chance of moisturepenetrating into or otherwise damaging the integrated circuit via thisarea.

The delamination area is located at or on a surface of the inner layer,as is the interface. It is favorable for the delamination area to have asize from 30 to 70 per cent. of the inner layer surface. Experience hasshown that such a proportion between the size of the delamination areaand the adhesive area works well. The optimum proportion is found to bedependent on the difference in coefficient of expansion between theinner and outer layer. Thus it may happen that there is adhesion onlyaround the connection regions of the integrated circuit. But this isalso amply sufficient. When the mechanical stresses can escape, there isno need to have the remaining portion of the inner layer adhere to theouter layer.

In an advantageous embodiment, an amount of hardened synthetic resin ispresent in the delamination area. The presence of such a synthetic resinis the result of an embodiment of the method according to the invention.The synthetic resin, for example an epoxy resin, an acrylate, or asilicone rubber, may be disposed in a simple manner on the inner layerwith a dispenser device, with an inkjet printer, or in some othermanner. After this the surfaces of the synthetic resin and of the innerlayer are activated. Then the outer layer is disposed. Since the portionof the surface covered by the synthetic resin is not activated, theadhesion between the synthetic resin and the inner layer is less goodthan the activated part. Alternatively, it is possible for the syntheticresin to be disposed only after the activation. In that case theadhesion between the synthetic resin and the outer layer is less good.When, the semiconductor device undergoes a subsequent soldering processat high temperature, the mechanical stresses will concentrate on thenon-activated surface of the synthetic resin. During this process thedelamination area is formed.

As an alternative to hardened synthetic resin some other material may beused which may be locally disposed on the inner layer and which has anat least relatively poor adhesion to the inner layer or to the outerlayer. It is then advantageous for the material to be disposed as afluid, but it is required that the material must not spread over thesurface of the inner layer. Furthermore it is required that the materialmust not expand substantially at the temperature of the solderingoperation.

It is preferred for the inner layer to leave the connection regionsuncovered. Such an embodiment of the semiconductor device is generallyknown and applicable in various ways. Known bonding means are, interalia, bond wires and globules of a conductive material such as solder.Alternatively, the inner layer itself is the bonding means. This is thecase when a capacitive or inductive coupling is used for the bondingbetween the integrated circuit and the carrier. This case is highlyadvantageous for identification purposes, where there is a limitedtransfer of data and energy. The carrier may comprise an antenna thatprovides a contactless coupling to a reading device.

In a further embodiment, the envelope is fixed to or on the carrier. Thecarrier of the semiconductor device according to the invention may be alead frame, or alternatively a printed circuit board, a ceramicsubstrate, or some other substrate. In this embodiment, which is alsoknown as a chip-scale package type, the outer layer of the cover is notprovided until the integrated circuit has been fixed to the substrate.The integrated circuit may then be connected to conductive parts on thecarrier by a ball-grid array type of bonding. It may also be that thesubstrate has an envelope consisting of an inner layer and an outerlayer. Owing to the great difference in thermal expansion between themostly silicon, substrate and the outer layer, it is advantageous alsoin this case that a delamination area is present.

It is a second object of the invention to provide a method of the typeset forth in the introductory section in which mechanical stresses canbe removed in a controlled manner.

The second object is achieved in that the activation of the surface ofthe inner layer takes place in accordance with to a pattern during whicha delamination area at or on the surface of the inner layer remainsinactivated. The patterned activation causes a delamination area toevolve. When mechanical stresses occur, they will be discharged bydelamination in the delamination area. The formation of microscopic andother cracks close to the connection regions is thus avoided or at leaststrongly reduced.

Activation in a pattern may be effected in various ways. In a firstembodiment, the activation takes place with light from a light source. Amask is positioned between the light source and the surface of the innerlayer during this. This mask may be installed in front of the lightsource. It may also be installed as a layer on top of the inner layer.An example of such a layer is a photoresist. The layer could be removedafter the activation has stopped. However, it is advantageous to providean amount of liquid material on the inner layer, which amount need notbe removed after the activation has stopped. It is an advantage of theamount of liquid material that the resulting delamination area has around, oval, or otherwise cornerless shape. Corners in the boundary areaof the delamination area form weak spots at which cracks may commence.Since an amount of a liquid material has a rounded surface, there isfurthermore a proper bonding to the outer layer.

In a second embodiment, the entire surface of the inner layer isactivated, after which a cover of the inner layer is provided locally.The cover is, for example, an amount of a liquid material. When theouter layer is subsequently applied, the adhesion between the cover andthe outer layer will be less strong than between the—activated—surfaceof the inner layer and the outer layer. This defines the delaminationarea.

By suitably positioning said amount, it is provided that thedelamination area is surrounded by areas with proper adhesion. Thelatter areas can convey the stress to the delamination area, whichstress has developed when the outer layer was disposed, which conveyanceis advantageous to the adhesion and reduces the risk of undesiredstresses. The positioning is preferably designed once and thereafterdetermined by the use of a template. On the other hand, it is possibleto utilize printing techniques in which the template is implemented inthe pattern on the stamp surface. A suitable example of such a printingtechnique is microcontact printing.

The liquid material is preferably provided in the form of a drop. Such adrop is provided, for example, disposed with a dispenser device. This ispreferred in that the amount of material can be set like by adapting thedispenser time, the diameter of the needle, or the application pressure.The liquid material is preferably a polymer that can be cured, such asan epoxy resin or an acrylate. The desired size and location of the dropdepends on the geometry of the design. The drop may be provided eitheron the lowerside or on the upper side, or on both sides of theintegrated circuit.

The inner layer preferably comprises a silicon material, which generallycomprises a dialkylsiloxane as a repetitive unit. Alternatively, apolyamide may be applied.

The curable material may be activated inter alia by means of a plasma ora corona treatment. A preferred embodiment is an oxygen plasmatreatment. This treatment may take place under atmospheric pressure aswell as under low pressure. It is an advantage of the treatment that itlasts only a few seconds.

These and further aspects of the semiconductor device and the methodaccording to the invention will be further explained with reference to adrawing and a description of the Figures, in which:

FIG. 1 is a diagrammatic cross-sectional view of the semiconductordevice;

FIG. 2 is a diagrammatic cross-sectional view of a detail of thesemiconductor device; and

FIG. 3 is a diagrammatic cross-sectional view of a second embodiment ofthe semiconductor device.

FIG. 1 is a diagrammatically a cross-sectional view of a semiconductordevice. An integrated circuit 10 made in and on a silicon substrate isconnected to a lead frame 14 by an adhesive layer 13 (for example silverpaste). The lead frame 14 usually consists of a FeNi or CuFe alloy. Theintegrated circuit is connected by bond wires 15 to the lead frame 14and is covered by an inner layer 21 of the envelope. This inner layer 21in this example comprises a silicone rubber. A passivation layer (notshown), usually silicon nitride, is located between the integratedcircuit 10 and the inner layer 21. The whole is encapsulated in an outerlayer 16 of the envelope, usually an epoxy resin filled with quartzpowder or glass powder.

FIG. 2 shows a detail of the semiconductor device shown in FIG. 1. Asilicon oxide layer 17 covers the integrated circuit 10. Aluminum bondpads 18 are located on the silicon oxide 17. The whole integratedcircuit is covered by a passivation layer 20 of silicon nitride withopenings provided at the bond pads. The thickness of the silicon nitridelayer is about 1 micrometer. The silicon nitride layer 20 is applied viaa PECVD process.

Subsequently, the silicon wafer comprising a plurality of integratedcircuits 10 with a silicon nitride layer 20 is divided into chips(dicing) which are mounted on the lead frame 14. Once the wires 15 havebeen connected to the lead frame 14 and the bonding pads 18, the wholeis covered with an inner layer 21 of poly(dimethylsiloxane). Then a dropof an epoxy resin from a dispenser device of the Varimeter/controllerTS9300 type from Techcon Systems Inc. is applied to the inner layer ofeach chip 10. Subsequently, the drop and the remaining surface areactivated by an oxygen plasma in a Tepla 300 microwave plasma systemunder a pressure of 1 or 2 mbar and at a power of 300 to 500 watts for 5to 10 seconds. Then the chip 10 is encapsulated in an epoxy resin 16. Tothis end, the customary filled epoxy resins can be applied such asEMF-6210 (suppliers Sumitomo). The drops result in a delamination area22 after a thermal treatment of the outer layer 16, which delaminationarea 22 is bounded by the mutual interface 24.

FIG. 3 shows a second embodiment of the semiconductor device accordingto the invention. The semiconductor device comprises a substrate of asemiconductor material, in this case Si, in which and on which anintegrated circuit 10 is provided. The integrated circuit 10 is coveredby a passivation layer 20 of silicon nitride which leaves bonding pads18 of Al exposed. On top of the passivation layer 20 lies the innerlayer 21 of polyamide. The bonding pads 18 are connected to solderglobules 30 via interconnects 28 and bridges 25 of a conductivematerial, for example Cu. Barrier layers 31 are located between thebridges 25 and the solder globules 30. The solder globules 30 makecontact with conductive portions 34 of the carrier 40.

The outer layer 16 is provided on top of the inner layer 21, the innerand outer layers 21, 16 having a mutual interface 24. A quantity ofmaterial that can be cured is also present on the inner layer 21. Afterthe soldering step this material will form the delamination area. As aresult of the temperature and pressure then occurring, the inner layer21 and the outer layer 16 are delaminated from each other in thedelamination area 22. In the Figure the delamination is indicated by adashed line 42. At the same time the mutual interface 24 between theinner layer 21 and the outer layer 16 is intact near the bridges 25 andthe interconnects 28.

Summarizing, a package of a semiconductor device comprising anintegrated circuit generally comprises an inner layer and an outerlayer, which layers have a mutual interface. An improved stability ofthe package is realized in that the interface encloses a delaminationarea, which area is isolated from any bonding pads of the integratedcircuit. The delamination can be created pattern-wise activation of asurface of the inner layer. Therefore, a quantity of a curable polymercan be disposed on this surface.

1. A semiconductor device (14, 40) comprising a carrier and anintegrated circuit (10) which: comprises one or more semiconductorelements and one or more connection regions (18) by which thesemiconductor elements are contacted, and is isolated from theenvironment by an envelope, said envelope comprising an inner layer (21)and an outer layer (16) which have a mutual interface (24), carrier (14,40) comprises electrically conductive portion (14, 34) by which theconnection regions (18) are connected via a connection means,characterized in that the mutual interface (24) fully bounds adelamination area (22), as a result of which full bounding thedelamination area (22) is isolated from the connection regions (18). 2.A semiconductor device as claimed in claim 1, characterized in that thedelamination area (22) and the interface (24) are located on a surfaceof the inner layer (21) and the delamination area (22) has a size ofbetween 30 and 70 per cent of the surface area of the inner layer (21).3. A semiconductor device as claimed in claim 1, characterized in thatthe inner layer (21) leaves the bonding pads (18) exposed.
 4. Asemiconductor device as claimed in claim 1, characterized in that aquantity of a cured synthetic resin is located in the delamination area(22).
 5. A semiconductor device as claimed in claim 1, characterized inthat the envelope is attached to or on the carrier.
 6. A semiconductordevice as claimed in claim 1, characterized in that the carrier (14) isa lead frame.
 7. A method of enveloping an integrated circuit in anenvelope comprising an inner layer (21) and an outer layer (16) whichhave a mutual interface (24), comprising the steps of: disposing theinner layer (21) on a surface of the integrated circuit; activating asurface of the inner layer (21), and disposing the outer layer (16) onthe surface of the inner layer (21), thus forming the mutual interface(24), characterized in that the surface of the inner layer (21) isactivated in accordance with a pattern, while a delamination area (22)at or on the surface of the inner layer (21) remains inactivated.
 8. Amethod as claimed in claim 7, characterized in that the patternedactivation is achieved by applying a quantity of a liquid material priorto the disposing of the outer layer (16), said quantity defining thedelamination area (22).
 9. A method as claimed in claim 8, characterizedin that the quantity of the liquid material which material is curable isas well, is applied before the surface of the inner layer (21) isactivated, while at the same time a surface of said quantity of materialis activated.
 10. A method as claimed in claim 7, characterized in thatthe activation takes place by means of a plasma treatment or a coronatreatment.